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CXD2450R
Timing Generator for Progressive Scan CCD Image Sensor
Description The CXD2450R is a timing generator IC which generates the timing pulses for performing progressive scan readout for digital still camera and personal computer image input applications using the ICX098AK CCD image sensor. This chip has a built-in vertical driver. Features * Base oscillation frequency 36.81MHz (2340fH) * Monitoring readout allowed * High-speed/low-speed electronic shutter function * Horizontal driver for CCD image sensor * Vertical driver for CCD image sensor * Signal processor IC system clock generation 1170fH, 780fH * Vertical/horizontal sync (SSG) timing generation Applications * Digital still cameras * Personal computer image input Structure Silicon gate CMOS IC Pin Configuration
EBCKSM HRO VDD6 VSS5 FRO SEN CLD SSK HRI RST
48 pin LQFP (Plastic)
Absolute Maximum Ratings * Supply voltage VDD VSS - 0.5 to +7.0 V VM VL - 0.5 to +26.0 V VH VL - 0.5 to +26.0 V VL VL - 0.5 to +26.0 V * Input voltage VI VSS - 0.5 to VDD + 0.5 V * Output voltage VO VSS - 0.5 to VDD + 0.5 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDDa, VDDb, VDDc, VDDd 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL -5.0 to -6.0 * Operating temperature Topr -20 to +75 Applicable CCD Image Sensors ICX098AK (1/4" CCD)
V V V V C
36 35 34 33 32 31 30 29 28 27 26 25 DSGAT 37 MCK 38 VM 39 V1 40 V3 41 V2a 42 VH 43 V2b 44 VSUB 45 VL 46 OSCO 47 OSCI 48 1 2 3 4 5 6 7 8 9 10 11 12 24 VDD5 23 3/2MCK 22 1/2MCK 21 PBLK 20 VSS4 19 XRS 18 XSHD 17 16 XSHP VDD4
FRI
SSI
15 XCLPDM 14 13 VDD3 H2
3MCK
VDD1
TEST
WEN
Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
XCLPOB
VDD2
VSS1
VSS2
VSS3
RG
H1
ID
-1-
E97819-PS
CXD2450R
Block Diagram
VDD3
VDD2
VDD4
XSHD
VSS3
XSHP
VSS2
14 OSCI 48
12 13
RG
H1
H2
11
8
9
10
16 17 18
19
20
OSCO
47 21 PBLK
VSS4
XRS
3MCK
1 1/2 1/2
1/3 Pulse Generator
15 XCLPDM 7 XCLPOB ID WEN
3/2MCK 23 1/2MCK 22
Latch
HRI differential Latch Latch SSG 1/390 V Driver
4 3
CLD 35 MCK 38 40 V1 42 V2a 44 V2b 41 V3 45 VSUB 43 VH 39 VM 46 VL
VDD1 VDD5 VDD6
6 24 26
VSS1 VSS5
2 1/2 36 Register 1/525
31
32
33
34
27
28 29 30
37
25
5
HRO
FRO
HRI
FRI
DSGAT
-2-
EBCKSM
TEST
SSK
SEN
RST
SSI
CXD2450R
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol 3MCK Vss1 WEN ID TEST VDD1 XCLPOB VDD2 RG Vss2 Vss3 H1 H2 VDD3 XCLPDM VDD4 XSHP XSHD XRS Vss4 PBLK 1/2MCK 3/2MCK VDD5 RST VDD6 SSI SSK SEN EBCKSM I/O I -- O O I -- O -- O -- -- O O -- O -- O O O -- O O O -- I -- I I I I Internal main clock. (2340fH) GND Memory write timing. Stop control possible using the serial interface data. Vertical direction line identification pulse output. Stop control possible using the serial interface data. IC test pin; normally fixed to GND. (With pull-down resistor) 3.3V power supply. (Power supply for common logic block) CCD optical black signal clamp pulse output. Stop control possible using the serial interface data. 3.3V power supply. (Power supply for RG) CCD reset gate pulse output. (780fH) GND GND CCD horizontal register clock output. (780fH) CCD horizontal register clock output. (780fH) 3.3V power supply. (Power supply for H1/H2) CCD dummy signal clamp pulse output. 3.3V power supply. (Power supply for CDS system) CCD precharge level sample-and-hold pulse output. (780fH) CCD data level sample-and-hold pulse output. (780fH) Sample-and-hold pulse output for analog/digital conversion phase alignment. (780fH) GND Pulse output for horizontal and vertical blanking interval pulse cleaning. Horizontal direction pixel identification pulse output. Stop control possible using the serial interface data. System clock output for signal processing IC. (1170fH) Stop control possible using the serial interface data. 3.3V power supply. (Power supply for common logic block) Internal system reset input. High: Normal status, Low: Reset status Always input one reset pulse after power-on. 3.3V power supply. (Power supply for common logic block) Serial interface data input for internal mode settings. Serial interface clock input for internal mode settings. Serial interface strobe input for internal mode settings. CHKSUM enable. (With pull-down resistor) High: Sum check invalid, Low: Sum check valid -3- Description
CXD2450R
Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Symbol FRO HRO HRI FRI CLD VSS5 DSGAT MCK VM V1 V3 V2a VH V2b VSUB VL OSCO OSCI
I/O O O I I O -- I O -- O O O -- O O -- O I
Description Vertical sync signal output. Stop control possible using the serial interface data. Horizontal sync signal output. Stop control possible using the serial interface data. Horizontal sync signal input. Vertical sync signal input. Clock output for analog/digital conversion IC. (780fH) Phase adjustment in 60 units possible using the serial interface data. GND Control input used to stop drive pulse generation for CCD image sensor, sample-and-hold IC and analog/digital conversion IC. High:Normal status,Low:Stop status Controlled pulse can be changed using the serial interface data. System clock output for signal processor IC. (780fH) GND (GND for vertical driver) CCD vertical register clock output. (Binary output) CCD vertical register clock output. (Binary output) CCD vertical register clock output. (Ternary output) 15.0V system power supply. (Power supply for vertical driver) CCD vertical register clock output. (Ternary output) CCD electronic shutter pulse output. -5.5V system power supply. (Power supply for vertical driver) Inverter output for oscillation. Inverter input for oscillation.
-4-
CXD2450R
Electrical Characteristics DC Characteristics Item Supply voltage 1 VDD2 Supply voltage 2 VDD3 Supply voltage 3 VDD4 Supply voltage 5 VH Supply voltage 6 VM Supply voltage 7 VL RST, DSGAT, Input voltage 11 SSI, SSK, SEN, FRI, HRI 1 , 2 EBCKSM Input voltage 2 Input voltage 32 TEST Output voltage 1 RG Output voltage 2 H1, H2 XSHP, XSHD, Output voltage 3 XRS, PBLK, XCLPDM Output voltage 4 3/2MCK, MCK, CLD Pins Symbol VDDa VDDb VDDc VH VM VL VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 VOH8 VOL8 VOM9 VOL9 VOH10 Output voltage 10 V2a, V2b Feed current where IOH = -3.3mA VDDa - 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = -10.4mA VDDb - 0.8 Pull-in current where IOL = 7.2mA Feed current where IOH = -3.3mA VDDc - 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = -10.4mA Pull-in current where IOL = 7.2mA Feed current where IOH = -3.3mA VDDd - 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = -2.4mA VDDd - 0.8 Pull-in current where IOL = 4.8mA Feed current where IOH = -3.6mA VDDd - 0.8 Pull-in current where IOL = 7.2mA Feed current where IOH = -4.0mA VH - 0.25 Pull-in current where IOL = 5.4mA Feed current where IOM = -5.0mA VM - 0.25 Pull-in current where IOL = 10.0mA Feed current where IOH = -7.2mA VH - 0.25 VM + 0.25 VL + 0.25 VL + 0.25 VL + 0.25 0.4 0.4 0.4 VDDd - 0.8 0.4 0.4 0.4 0.4 0.7VDDd 0.3VDDd 0.8VDDd 0.2VDDd (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 3.0 14.5 -- -6.0 0.8VDDd 0.2VDDd Typ. 3.3 3.3 3.3 3.3 15.0 0.0 -5.5 Max. 3.6 3.6 3.6 3.6 15.5 -- -5.0 Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
Supply voltage 4 VDD1, VDD5, VDD6 VDDd
Output voltage 5 1/2MCK Output voltage 6 XCLPOB, ID, WEN
Output voltage 7 FRO, HRO Output voltage 8 VSUB Output voltage 9 V1, V3
VOM101 Pull-in current where IOM = 5.0mA VOM102 Feed current where IOM = -5.0mA VM - 0.25 VOL10 Pull-in current where IOL = 10.0mA
1 These input pins do not have protective diodes on the internal power supply side. 2 These input pins have internal pull-down resistors. 3 The above table indicates the condition for 3.3V drive of low voltage drive blocks. -5-
CXD2450R
Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Pins OSCI OSCI Symbol LVth VIH VIL VOH Output voltage OSCO VOL Feedback resistor Oscillation frequency OSCI, OSCO RFB OSCI, OSCO f
(Within the recommended operating conditions) Conditions Min. Typ. VDDd/2 0.7VDDd 0.3VDDd Feed current where IOH = -6.0mA Pull-in current where IOL = 6.0mA VIN = VDDd or Vss 500k 20 2M VDDd/2 VDDd/2 5M 50 Max. Unit V V V V V MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplification 3MCK Pins Symbol LVth VIH VIL VIN fmax 50MHz sine wave 0.3 0.7VDDd 0.3VDDd Conditions Min. Typ. VDDd/2 Max. Unit V V V Vp-p
1 Input voltage is the input voltage characteristics for direct input from an external source. Input amplification is the input amplification characteristics in the case of input through capacitor. Switching Characteristics Item Symbol TTLM Rise time TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Conditions (VH = 15.0V, VM = GND, VL = -5.5V) Min. -- -- -- -- -- -- -- -- -- -- Typ. 150 150 50 100 150 50 -- -- -- -- Max. 300 300 100 200 300 100 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V
1 The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2 For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1F or more) between each power supply pin (VH, VL) and GND. -6-
CXD2450R
Switching Waveforms
TTMH 90% TTHM VH 90%
V2a (V2b)
TTLM 90%
10%
10%
TTML VM 90%
10%
10%
VL
TTLM 90% V1 (V3) 10%
TTML VM 90% 10% VL
TTLH
TTHL VH 90% 90%
VSUB
10%
10%
VL
Waveform Noise
VH
VCMH
VCML
VCLH
VCLL VL
-7-
CXD2450R
Measurement Circuit
Serial interface data
+3.3V -5.5V +15.0V 36 C1 R1 C1 R1 C1 R2 C3 48 1 12 13 C5 C2 C2 C2 C2 R1 C1 R1 C6 C6 C6 37 25 24
3MCK C4 C5
R1: 68W R2: 15W
C1: 450pF C2: 2200pF C3: 500pF
C4: 30pF C5: 100pF C6: 10pF
-8-
CXD2450R
AC Characteristics 1) AC characteristics between the serial interface clocks
SSI SSK SEN SEN ts2 0.8VDDd 0.2VDDd 0.8VDDd 0.2VDDd ts1 0.2VDDd ts3 0.8VDDd th2 th1
(Within the recommended operating conditions) Symbol Definition SSI setup time, activated by the rising edge of SSK SSI hold time, activated by the rising edge of SSK SSK setup time, activated by the rising edge of SEN SSK hold time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SSK Min. 20 20 20 20 20 Typ. Max. Unit ns ns ns ns ns
ts1 th1 ts2 th2 ts3
2) Serial interface clock internal loading characteristics
Example: During recording drive mode FRI HRI
V2a Enlarged view HRI V2a ts4 SEN 0.8VDDd 0.2VDDd th4 0.2VDDd
Note) Be sure to maintain a constantly high SEN logic level near the falling edge of HRI immediately before the readout period. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of HRI SEN hold time, activated by the falling edge of HRI -9- Min. 0 0 Typ. Max. Unit ns ns
ts4 th4
CXD2450R
3) Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD2450R at the timing shown in 2) above. However, one exception to this is when the data such as SSGSEL and STB is loaded to the CXD2450R and controlled at the rising edge of SEN. For STB, see control data D62 to D63 STB in "Description of Operation".
SEN Output signal
0.8VDDd
tpdPULSE
(Within the recommended operating conditions) Symbol Definition Output signal delay, activated by the rising edge of SEN Min. 5 Typ. Max. 100 Unit ns
tpdPULSE
4) RST loading characteristics
RST
0.8VDDd 0.2VDDd tw1
(Within the recommended operating conditions) Symbol Definition RST pulse width Min. 35 Typ. Max. Unit ns
tw1
5) Phase discrimination characteristics using FRI and HRI input
When the HRI logic level is low tpd1 after the falling edge of FRI When the HRI logic level is high tpd1 after the falling edge of FRI
FRI HRI
0.2VDDd tpd1
FRI HRI
0.2VDDd tpd1
The field is discriminated as an ODD field .
The field is discriminated as an EVEN field .
(Within the recommended operating conditions) Symbol Definition Field discrimination clock phase, activated by the falling edge of FRI Min. 1100 Typ. Max. 1300 Unit ns
tpd1
- 10 -
CXD2450R
6) FRI and HRI loading characteristics
FRI, HRI
0.2VDDd ts5 th5
0.2VDDd
MCK
0.8VDDd
MCK load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition FRI and HRI setup time, activated by the rising edge of MCK FRI and HRI hold time, activated by the rising edge of MCK Miin. 10 0 Typ. Min. Unit ns ns
ts5 th5
7) Output timing characteristics using DSGAT
DSGAT H1, H2, RG, XSHP, XSHD, XRS, PBLK, XCLPDM, XCLPOB, CLD
0.2VDDd 0.2VDDd tpDSGAT
However, V2a, V2b and VSUB are fixed to the voltage level applied to the VH pin, and V1 and V3 are fixed to the voltage level applied to the VM pin. H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF, XSHP, XSHD, XRS, PBLK, XCLPDM, XCLPOB and CLD load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition Time until the above outputs go low after the fall of DSGAT Miin. Typ. Min. 100 Unit ns
tpDSGAT
8) Output variation characteristics
MCK WEN, ID
0.8VDDd
tpd2
WEN and ID load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition Time until the above outputs change after the rise of MCK - 11 - Miin. 20 Typ. Min. 40 Unit ns
tpd2
CXD2450R
9) H1 and RG waveform characteristics
0.9VDDb H1 0.1VDDb 0.9VDDa RG 0.1VDDa trRG 0.1VDDa tfRG trH1 tfH1 0.9VDDa 0.1VDDb 0.9VDDb
VDDb = 3.3V, Topr = 25C, H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF (Within the recommended operating conditions) Symbol Definition H1 rise time H1 fall time RG rise time RG fall time Min. Typ. 10 10 3 3 Max. Unit ns ns ns ns
trH1 tfH1 trRG tfRG
10) I/O pin capacitance Symbol CIN COUT CI/O Input pin capacitance Output pin capacitance I/O pin capacitance Definition
(Within the recommended operating conditions) Min. Typ. Max. 9 11 11 Unit pF pF pF
- 12 -
CXD2450R
Description of Operation Pulses output from the CXD2450R are controlled by the RST and DSGAT pins and by the serial interface data shown below. The details of control by the serial interface data and a description of operation are as follows.
SSI
00 01 02 03 04 05 06 07 08 09 10 11
58 59 60 61 62 63 64 65 66 67 68 69 70 71
SSK
SEN
The CXD2450R basically loads and reflects the serial interface data sent in the above format in the readout portion at the falling edge of HRI. Here, readout portion specifies the horizontal interval during which V2a and V2b take the ternary level. There are two types of serial interface data: drive control data and phase adjustment data. Hereafter, these data are distinguished by referring to the former as control data and the latter as adjustment data. An example of the initialization data for the CXD2450R control data is shown below. This data is based on the Application Circuit Block Diagram, so care should be taken as there are some differences from the RST pin initialization data. Concretely, the internal SSG operates, the XCLPOB and ID pulses are generated, and the 3/2MCK pulse is stopped. This data shows the values when the EBCKSM pin is low and D64 to D71 CHKSUM is valid. MSB D71 D70 1 0 MSB D55 D54 1 1 MSB D39 D38 0 0 MSB D23 D22 0 0 MSB D07 D06 1 0 LSB D56 0 LSB D40 0 LSB D24 0 LSB D08 0
D69 1 D53 0 D37 0 D21 0 D05 0
D68 0 D52 1 D36 0 D20 0 D04 0
D67 1 D51 0 D35 0 D19 0 D03 0
D66 1 D50 0 D34 0 D18 0 D02 0
D65 0 D49 0 D33 0 D17 0 D01 0
D64 1 D48 0 D32 0 D16 0 LSB D00 1
D63 0 D47 0 D31 0 D15 0
D62 0 D46 0 D30 0 D14 0
D61 0 D45 0 D29 0 D13 0
D60 0 D44 0 D28 0 D12 0
D59 0 D43 0 D27 0 D11 0
D58 0 D42 0 D26 0 D10 0
D57 1 D41 0 D25 0 D09 0
The adjustment data does not normally need to be set. However, when adjustment is difficult due to the system configuration or for other reasons, the data considered most appropriate at that time should be set as the initialization data.
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CXD2450R
Control Data Data D00 to D07 D08 to D15 D16 to D17 D18 to D25 D26 to D35 D36 to D47 D48 D49 to D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 to D61 D62 to D63 D64 to D71 Symbol CHIP Function Chip switching Data = 0 Data = 1 When a reset All 0
See D00 to D07 CHIP.
CTGRY
Category switching
See D08 to D15 CTGRY.
All 0
SMD
Electronic shutter mode setting
See D16 to D35 Electronic shutter mode. See D16 to D35 Electronic shutter mode. See D16 to D35 Electronic shutter mode.
All 0
Shut.FRM
Electronic shutter vertical interval setting Electronic shutter horizontal interval setting
All 0
Shut.HD
All 0
-- EXPOSE -- PSMT SSGSEL WENSEL CLPSEL IDSEL HMCKSEL TMCKSEL HMCKREV TMCKREV DSG
-- Recording exposure setting switching -- Drive mode switching Internal SSG operation switching WEN pulse operation switching XCLPOB pulse operation switching ID pulse operation switching 1/2MCK pulse operation switching 3/2MCK pulse operation switching
-- OFF -- Monitoring OFF ON OFF OFF OFF ON
-- ON -- Recording ON OFF ON ON ON OFF
All 0 0 All 0 0 0 0 0 0 0 0 0 0 All 0
1/2MCK pulse reset polarity switching Positive polarity Negative polarity 3/2MCK pulse reset polarity switching Negative polarity Positive polarity Pulse generation control See D60 to D61 DSG table.
STB
IC pin status control
See D62 to D63 STB table.
All 0
CHKSUM
Check sum bit
See D64 to D71 CHKSUM.
All 0
- 14 -
CXD2450R
Detailed Description of Each Data D00 to D07 CHIP The serial interface data is loaded to the CXD2450R when D00 and D07 are 1. However, this assumes that either the EBCKSM pin is low and D64 to D71 CHKSUM is satisfied or the EBCKSM pin is high. MSB D07 D06 1 0 LSB D00 1 Function Loading to the CXD2450R
D05 0
D04 0
D03 0
D02 0
D01 0
Note that when SEN is shared with other ICs and identification is performed using CHIP-ID, the CXD2450R data must be positioned immediately before the load timing, that is to say at the very end. D08 to D15 CTGRY Of the data provided to the CXD2450R by the serial interface, the CXD2450R loads D16 and subsequent data to the control data register side when D08 is 0, and to the adjustment data register side when D08 is 1. However, this assumes that the CXD2450R is selected by CHIP and that either the EBCKSM pin is low and D64 to D71 CHKSUM is satisfied or the EBCKSM pin is high. MSB D15 D14 0 0 0 0 LSB D08 0 1 Function Loading to the control data register side Loading to the adjustment data register side
D13 0 0
D12 0 0
D11 0 0
D10 0 0
D09 0 0
Note that the CXD2450R cannot apply both categories simultaneously during the same vertical interval. Also, care should be taken as the data is overwritten even if the same category is applied. D16 to D35 Electronic shutter mode The CXD2450R's electronic shutter mode can be switched as follows by SMD D16 to D17 . Handling of the data from D18 to D35 differs according to the mode, and is explained in detail below. D17 X 0 1 D16 0 1 1 Description of operation VSUB stopped mode High-speed/low-speed shutter mode HTSG control mode
The electronic shutter data is expressed as shown in the table below using Shut.HD as an example. MSB D35 0 1 D34 1 D33 1 D32 1 C D31 0 D30 0 D29 0 D28 0 3 D27 1 LSB D26 1 Shut.HD is expressed as 1C3h .
[VSUB stopped mode] During this mode, the data from D18 to D35 is invalid. The shutter speed is 1/60 s during monitoring drive mode, and 1/30 s during recording drive mode. - 15 -
CXD2450R
[High-speed/low-speed shutter mode] During this mode, the data has the following meanings. Symbol Shut.FRM Shut.HD Data D18 to D25 D26 to D35 Description Shutter speed data (number of vertical intervals) specification Shutter speed data (number of horizontal intervals) specification
The CXD2450R does not distinguish between the high-speed shutter and low-speed shutter modes. The interval during which Shut.FRM and Shut.HD are specified together is the shutter speed. At this time, Shut.FRM controls the ternary level output at V2a and V2b, and Shut.HD controls the VSUB output. Concretely, when specifying high-speed shutter, Shut.FRM is set to 00h. (See the figure.) During low-speed shutter, or in other words when Shut.FRM is set to 01h or higher, the serial interface data is not loaded until this interval is finished. However, care should be taken as the vertical interval indicated here is set in 1/60s units when the drive mode is monitoring drive mode and 1/30s units during recording mode. For monitoring drive mode, care should be taken as the Shut.HD value has an offset. This is so that the CXD2450R can obtain basically the same exposure time for the same Shut.HD value during high-speed shutter independent of the drive mode. Formula for calculating the electronic shutter speed: [Shut.FRM/Shut.HD] (unit: s) Monitoring drive mode: T = Shut.FRM1.66834104 + {(20Ch - Shut.HD)780 + 447} 81.510-3 (000h Shut.HD 20Ch)
FRI
V2a Shut.HD-106h VSUB SMD Shut. FRM Shut. HD WEN 01 00h 1A6h 01 01h 1DDh 01 00h 1A6h Shut.FRM
During monitoring drive mode/low-speed shutter mode
Recording drive mode: T = Shut.FRM3.33667104 + {(20Ch - Shut.HD)780 + 447} 81.510-3 (000h Shut.HD 20Ch)
FRI
V2a Shut.HD VSUB Shut.FRM
SMD Shut. FRM Shut. HD WEN
01 01h 1DDh
01 00h 1A6h
During recording drive mode/low-speed shutter mode - 16 -
CXD2450R
Electronic shutter speed table [Shut.FRM/Shut.HD] Shut.FRM Shut.HD 00h 00h 00h 00h 00h 00h 00h 00h 00h 20Ch 20Bh 209h 205h 1FDh 1EDh 1CEh 18Fh 16Fh Shutter speed (s) Calculation results (s) Shut.FRM Shut.HD Shutter speed (s) Calculation results (s) 00h 1/27000 1/27450 107h1 1/60 1/60 01h 1/10000 1/10000 20Ch 1/602 1/60 2 01h 1/4500 1/4403 1D8h 1/50 1/50 1/2000 1/1000 1/500 1/250 1/125 1/100 1/2077 1/1010 1/498 1/251 1/125 1/100 02h 07h 09h 00h 00h 00h 20Ch 18Bh 109h 0D2h 083h 000h 1/302 1/82 1/62 1/503 1/403 1/303 1/30 1/8 1/6 1/50 1/40 1/30
1 One VSUB pulse is generated for odd fields and two for even fields. 2 These are the settings during monitoring drive mode. 3 These are the settings during recording drive mode. Note) Input prohibited data: Monitoring drive mode Recording drive mode and monitoring drive mode
000h to 106h 20Dh to 3FFh
[HTSG control mode] During this mode, the data from D18 to D35 is invalid. The ternary level outputs at V2a and V2b are controlled, and the shutter speed is the value obtained by adding the shutter speed specified in the preceding vertical interval to the vertical period during which V2a and V2b are stopped as shown in the figure.
FRI
V2a VSUB Vck SMD WEN 01 11 01
During HTSG control mode
- 17 -
CXD2450R
D48 EXPOSE 0: No operation 1: VSUB for recording exposure is generated. This control specification is such that one VSUB pulse is always generated during the horizontal interval immediately following the readout portion even if the electronic shutter speed is set to 1/60s (SMD = 00). This mode is closely related to D51 PSMT, so see D51 regarding the control. D51 PSMT 0: Driving is controlled in accordance with monitoring drive mode under the assumption that the vertical/ horizontal sync signals are input. 1: Driving is controlled in accordance with recording drive mode under the assumption that the vertical/ horizontal sync signals are input. See the timing charts for the vertical/horizontal sync signals in accordance with each mode. Note that when switching from monitoring drive to recording drive mode, the pixels decimated thus far must be cleaned. Concretely, this operation is supported by generating VSUB, but the CXD2450R facilitates this control by using D48 EXPOSE. (See the figure.)
FRI
V2a VSUB
Exposure time WEN SMD EXPOSE PSMT Mode 00 0 0 Monitoring 00 1 0 Monitoring 00 0 1 Recording 00 0 0 Monitoring
Image of switching from monitoring drive mode to recording drive mode D52 SSGSEL 0: Internal SSG functions are stopped. 1: Internal SSG functions operate, and FRO and HRO are generated. When generation is stopped, these pulses are fixed low. D53 WENSEL 0: WEN is generated. 1: WEN generation is stopped. When generation is stopped, operation is the same as for D52 SSGSEL. - 18 -
CXD2450R
D54 CLPSEL 0: XCPOB generation is stopped. 1: XCPOB is generated. When generation is stopped, operation is the same as for D52 SSGSEL. D55 IDSEL 0: ID generation is stopped. 1: ID is generated. When generation is stopped, operation is the same as for D52 SSGSEL. D56 HMCKSEL 0: 1/2MCK generation is stopped. 1: 1/2MCK is generated. When generation is stopped, operation is the same as for D52 SSGSEL. D57 TMCKSEL 0: 3/2MCK is generated. 1: 3/2MCK generation is stopped. When generation is stopped, operation is the same as for D52 SSGSEL. D58 HMCKREV 0: 1/2MCK reset when positive polarity. 1: 1/2MCK reset when negative polarity. D59 HMCKREV 0: 3/2MCK reset when negative polarity. 1: 3/2MCK reset when positive polarity.
D60 to D61 DSG The CXD2450R can apply stop control to the CCD pulses and pulses for the sample-and-hold and analog/digital conversion ICs by setting the DSGAT pin low. Conversely, when the DSGAT pin is set high, the controlled pulses can be switched as follows using the serial interface data. D61 0 0 1 1 D60 0 1 0 1 No control performed CCD pulse stop control Sample-and-hold and analog/digital conversion IC pulse stop control CCD pulse and sample-and-hold and analog/digital conversion IC pulse stop control Operating mode
Here, CCD pulses refer to the H1, H2, RG, V1, V2a, V2b, V3 and VSUB pulses. Sample-and-hold and analog/digital conversion IC pulses refer to the XSHP, XSHD, XRS, PBLK, XCLPOB, XCLPDM and CLD pulses. See 7) Output timing characteristics using DSGAT of "AC Characteristics" for the stop control status of each pulse. - 19 -
CXD2450R
D62 to D63 STB This switches the operating mode as shown below. However, the IC pin status control bit is loaded to the CXD2450R and controlled immediately at the rise of the SEN input. D63 X 0 1 D62 0 1 1 Symbol CAMERA SLEEP STNBY Operating mode Normal operating mode Sleep mode1 Standby mode
1 Mode for the status which does not require CCD drive when playing back recorded data within the system. The pin status during each mode is shown in the table below. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol 3MCK Vss1 WEN ID TEST VDD1 XCLPOB VDD2 RG Vss2 Vss3 H1 H2 VDD3 XCLPDM VDD4 XSHP XSHD XRS Vss4 PBLK 1/2MCK 3/2MCK VDD5 ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT CAMERA ACT SLEEP ACT -- L L -- -- L -- L -- -- L L -- L -- L L L -- L L ACT -- L L L L L L L L L L L L L STNBY ACT Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol RST VDD6 SSI SSK SEN EBCKSM FRO HRO HRI FRI CLD Vss5 DSGAT MCK VM V1 V3 V2a VH V2b VSUB VL OSCO OSCI ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT CAMERA ACT SLEEP ACT -- ACT ACT ACT ACT ACT ACT ACT ACT L -- ACT ACT -- VM VM VH -- VH VH -- ACT ACT ACT ACT VH VH VM VM VH ACT L ACT ACT ACT ACT L L ACT ACT L STNBY ACT
Note) ACT means that the circuit is operating. L indicates a low output level in the controlled status. Also, VH and VM indicate the voltage levels applied to VH (Pin 43) and VM (Pin 39), respectively, in the control status. - 20 -
CXD2450R
D64 to D71 CHKSUM This is the check sum bit. Apply the data shown below. MSB D07 D15 D23 D31 D39 D47 D55 D63 +) D71 0 LSB D00 D08 D16 D24 D32 D40 D48 D56 D64 0
D06 D14 D22 D30 D38 D46 D54 D62 D70 0
D05 D13 D21 D29 D37 D45 D53 D61 D69 0
D04 D12 D20 D28 D36 D44 D52 D60 D68 0
D03 D11 D19 D27 D35 D43 D51 D59 D67 0
D02 D10 D18 D26 D34 D42 D50 D58 D66 0
D01 D09 D17 D25 D33 D41 D49 D57 D65 0
CHKSUM Reflected when the total is 0.
- 21 -
Chart-1
Vertical Direction Timing Chart
MODE (Base oscillation frequency: 2340fH) Recording drive mode
Applicable CCD image sensor: ICX098AK
FRI
525 1 525 1
HRI VSUB V1
V2a
V2b
- 22 -
V3
R BR 2 3 BR 4 5 BR 6 7 B 8 BRB R B 2 1 2 3 4 5 6 7 8 R 1
CCD OUT PBLK XCLPOB XCLPDM ID WEN
1
2
3
4
5
6
7
8
1
490491492493494 1
The number of VSUB pulses is determined by the serial interface data. This chart shows the case where Shut.HD = 20Ch and VSUB pulses are generated over the entire horizontal interval. In addition to the phase relationship between FRI and HRI shown above, the phases may also be offset by 1/2 horizontal interval. In any case, the readout interval is the 9th HRI fall counted from the fall of FRI. Note that R and B of CCDOUT indicate lines containing these components, and do not mean the lead pixel component of that line.
CXD2450R
Chart-2
Vertical Direction Timing Chart
MODE (Base oscillation frequency: 2340fH) Monitoring drive mode
Applicable CCD image sensor: ICX098AK
FRI
525 1 262
HRI VSUB
V1
V2a
V2b V3
B RB RBR B 1 2 5 6 RB 1 2 RB 5 6 RB RB RB RB RB R B RB RB RB RB RB RB RB 1 2 5 6 RB 1 2 RB 5 6 RBR B
- 23 -
CCD OUT PBLK XCLPOB XCLPDM ID WEN
482 485486489490493494
9 10 13 14 17 18 21 22 25 26 29
466469470473474 477478 481482485486489490 493494
9 10 13 14
The number of VSUB pulses is determined by the serial interface data. This chart shows the case where Shut.HD = 20Ch and VSUB pulses are generated over the entire horizontal interval. Note that R and B of CCDOUT indicate lines containing these components, and do not mean the lead pixel component of that line.
CXD2450R
Chart-3
Horizontal Direction Timing Chart
MODE (Base oscillation frequency: 2340fH) Recording drive mode
Applicable CCD image sensor: ICX098AK
0 HRI MCK
BB BB BBB BB G GGG GGG GG
50
100
550
43 44 80 56 92 92 68 104 81 104
116
GG R RR
G GGG GGG GGG GGG GGG GGG GGG GGG GGG GGG GGG GGG GGG GG R R R R R R R R R R R RR R R R R R R R RR R R R R R R R R R R R R R R R R RR R R
H1 V1 V2a
56
V2b V3
- 24 -
VSUB
44 129
PBLK
21 40 118 129
XCLPOB XCLPDM
68
ID
68
WEN
The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates the actual CXD2450R load timing. The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI. The HRI fall interval should be between 3.6 to 9.4s. This chart shows an interval of 78ck (6.3s). VSUB is output at the timing shown above when specified by the serial interface data. The ID transition timing is synchronized with the rise of V3. WEN is output during the horizontal interval shown in Chart-1. The transition timing is the same as that for ID. R, G and B of H1 indicate the output pixel color. In addition to the lines starting from R and G shown above, there are also lines starting from G and B.
CXD2450R
Chart-4
Horizontal Direction Timing Chart
MODE (Base oscillation frequency: 2340fH) Recording drive mode (readout portion)
Applicable CCD image sensor: ICX098AK
0 HRI MCK
43
50
100
550
116 80 116 521 520 56 92 520 56 92 551
H1
44
V1
V2a
551
V2b
68 104
- 25 -
V3
81 104
VSUB PBLK
21 40 118 129
XCLPOB XCLPDM
68
ID
68
WEN
The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates the actual CXD2450R load timing. The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI. The HRI fall interval should be between 3.6 to 9.4s. This chart shows an interval of 78ck (6.3s). VSUB is output at the timing shown above when specified by the serial interface data. The ID transition timing is synchronized with the rise of V3. ID is reset low at this timing during the readout horizontal interval. WEN is output during the horizontal interval shown in Chart-1. The transition timing is the same as that for ID.
CXD2450R
Chart-5
Horizontal Direction Timing Chart
MODE (Base oscillation frequency: 2340fH) Monitoring drive mode
Applicable CCD image sensor: ICX098AK
0 HRI MCK
BB B B BB B B B G GG G G G G G G
50
100
550
43 44 62 50 68 80 86 98 104
116
GG R RR
GGG GGG GGG GGG GGG GGG GGG GGG GGG GGG GGG GGG GGG GGG RRR RRR RRR RRRR RRR RRR RRR RRR RRR RRR RRR RRR RRR RR
H1 V1 V2a
50 68 58 74 86 92 104 110
V2b V3
81 104
- 26 -
VSUB
44 129
PBLK
21 40 118 129
XCLPOB XCLPDM
92
ID
92
WEN
The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates the actual CXD2450R load timing. The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI. The HRI fall interval should be between 3.6 to 9.4s. This chart shows an interval of 78ck (6.3s). VSUB is output at the timing shown above when specified by the serial interface data. The ID transition timing is synchronized with the rise of V3. WEN is output during the horizontal interval shown in Chart-2. The transition timing is the same as that for ID. R, G and B of H1 indicate the output pixel color. In addition to the lines starting from R and G shown above, there are also lines starting from G and B.
CXD2450R
Chart-6
Horizontal Direction Timing Chart
MODE (Base oscillation frequency: 2340fH) Monitoring drive mode (readout portion)
Applicable CCD image sensor: ICX098AK
0 HRI MCK
43
50
100
550
116 62 80 98 116 521
H1
44
V1
520 50 68 86 104 551
V2a
50 68 86 104
V2b
- 27 -
58
74
92
110
V3
81 104
VSUB PBLK
21 40 118 129
XCLPOB XCLPDM
92
ID
92
WEN
The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates the actual CXD2450R load timing. The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI. The HRI fall interval should be between 3.6 to 9.4s. This chart shows an interval of 78ck (6.3s). VSUB is output at the timing shown above when specified by the serial interface data. The ID transition timing is synchronized with the rise of V3. ID is reset low at this timing during the readout horizontal interval. WEN is output during the horizontal interval shown in Chart-2. The transition timing is the same as that for ID.
CXD2450R
Chart-7
High-speed Phase Timing Chart
MODE (Base oscillation frequency: 2340fH)
Applicable CCD image sensor: ICX098AK
HRI HRI' 3MCK 3/2MCK 1/2MCK CLD
43 116
MCK
- 28 -
H1 H2 RG XSHP XSHD XRS
HRI' indicates the HRI which is the actual CXD2450R load timing. The 3/2MCK and 1/2MCK polarities can be inverted by the serial interface data. This chart indicates the status in which 3/2MCK is negative polarity and 1/2MCK is positive polarity.
CXD2450R
CXD2450R
Application Circuit
Block Diagram
CCD ICX098AK
CCD OUT
S/H CXA2006Q
DRV OUT VRT VRB
A/D CXD2310AR
D0 to 9
10
XCLPDM
XSHP
XCLPOB
XSHD
XRS
PBLK
17 18 19 21 15 H1 H2 RG 12 13 9
7
CLD
35 23 22 4 3 ID WEN MCK FRI HRI HRO FRO Signal Processor Block 3/2MCK 1/2MCK 38 34 33 32 SSG 31 27 28 29
V1 V2a V2b V3 VSUB
40 42 44 41 45 1 47 48 V-Dr
TG CXD2450R
25 37 5 30
SSI
EBCKSM
OSCI RST
3MCK OSCO
DSGAT
TEST
SEN
SSK
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes for Power-on Of the three -5.5V, +15.0V and +3.3V power supplies, be sure to start up the -5.5V and +15.0V power supplies in the following order to prevent the VSUB pin of the CCD image sensor from going to negative potential.
15.0V
t1
20% 0V 20%
t2 t2 t1
-5.5V
- 29 -
CXD2450R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24
(8.0)
A 48 1 0.5 0.08 + 0.08 0.18 - 0.03 0.1 0.1 + 0.2 1.5 - 0.1 12 13
(0.22)
+ 0.05 0.127 - 0.02 0.1
0 to 10
0.5 0.2
NOTE: "" Dimensions do not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 QFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g
- 30 -
0.5 0.2

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